Microprocessor chips fabricated with current CMOS technology are designed with great care to comprehend the circuit performance variations that occur as the process shifts from one tolerance extreme to the other. Designers have become accustomed to speak of MOS transistors having maximum drive capability as strong transistors and MOS transistors with minimum drive capability as weak transistors. At both of these extremes, the transistors are within specified process tolerance limits. It is desirable to maximize the useable yield of all functional devices even though different speed performance devices will be produced. Normally the whole performance distribution is salable.
In practice, designs are analyzed according to (a) transistor strength, (b) power supply voltage tolerances, (c) interconnect resistance and capacitance, and (d) operating temperature, among other possible parameters. Logic portions of the circuit must match as closely as possible the memory portions of the circuit and the interface should be optimized on every die as much as practical.
Experience has shown that to optimize overall yield, both memory designs and logic designs should carried out for highest possible speed performance considering all the design parameters. The most effective matching between elements of the logic and elements of memory has been shown to be achievable by adjusting memory performance downward incrementally as necessary to improve to usability of the full performance spread of the logic circuit portions. Hence, memory designers have conventionally designed-in memory trimming circuitry to incrementally lower the speed of the memory function. These memory trimming circuits are generally used to adjust the propagation delays in the read and write control circuits and have in some cases also been applied to adjustment of memory sense amplifier reference elements.
Pervious Techniques for Memory Trimming
Originally, memory trimming was achieved by utilizing spare gates by way of a revision of the chip interconnect pattern. This incurs significant costs and cycle times to produce revised photomask reticles and to complete fabrication of the revised product.
A later technique introduced to make memory trimming more practical laser fuses. Laser fuses built into the die may be blown to achieve many of the desired memory trimming adjustments. However, laser fuses must be large in chip area to ensure dependable laser beam hits.
Electrical Fuses for Programming
Electrical fuses (eFuses) are extremely attractive for this kind of application and have made a great impact on digital processor devices. Originally eFuses were applied to the obvious need for device programmability. The possibility of programming a device to do a specific task efficiently has made modest cost special purpose processors a reality. Many fusible interconnect links are constructed of materials such as deposited amorphous polysilicon.
These electrical fuses (eFuses) in VLSI silicon devices are programmed conventionally by applying a relatively large amount of power to the fuse body to melt and separate the fuse body material. This changes the eFuse resistance from a low pre-blow resistance to a high post-blow resistance. This result can be sensed to determine the state of the eFuse: unblown or blown.
Efuse Implementation
The eFuse for a conventional programmable device application is normally configured as a chain or two-dimensional array sometimes containing hundreds of eFuses and supporting logic. Several definitions will be helpful in clarifying the descriptions of eFuse implementation to follow.
1. The eFuse is a circuit element having a natural un-programmed state, but may be permanently programmed to the opposite state.
2. An eFuse element is an eFuse along with its programming and sensing circuits.
3. An eFuse cell is an eFuse element plus the local logic required to integrate it into an eFuse chain.
4. An eFuse chain is a collection of one or more eFuse cells connected in series or arrays.
5. An eFuse controller is the control logic designed to access the eFuse chains or arrays.
6. An un-programmed eFuse has a pre-defined maximum low resistance value.
7. A programmed eFuse has a pre-defined minimum high resistance value.
The eFuse chain is programmed by loading the desired fused state and non-fused state locations into a programming database containing a record for the individual elements of the entire chain. Then those values are programmed into each eFuse sequentially.
FIG. 1 illustrates the conventional eFuse cell circuit configuration, which includes an eFuse element 101 plus the local logic required to integrate it into an eFuse chain. CData flip-flop 103 is clocked by the Enable Clock 108 and stores cell data in the chain. PData flip-flop 102 is clocked by the Data Clock 106 and latches program data being passed into the eFuse cell.
In the program mode, incoming PData In 107 is latched into PData flip-flop 102. This data is programmed into the eFuse element on the occurrence of one or more program pulses at Program input 110. PData Out 116 passes to the eFuse cell via path 116. In the program mode, PData Out passes through multiplexers 104 and 105 and is latched into the CData flip-flop 102. VPP 109 is the programming power source input. Program data is passed serially to the next cell in the chain at PData Out line 116.
In the test mode, the CData flip-flop 103 latches the data from the present cell and passes it to Cell Data Out 115. This data from the present cell is passed through multiplexer 104 and multiplexer 105 as directed by Test input 111.
Initz input 112 acts to initialize all flip-flops in the cell chain prior to the programming cycle. Margin input 114 allows adjustment of the reference input for a differential amplifier so that the desired high resistance values specified for a program element may be modified.
FIG. 2 illustrates a simplified view of a conventional eFuse system having an eFuse controller 200 and a number of series-connected eFuse cells 201 through 205. Each cell 201 through 205 has the local logic of FIG. 1 for integrating the cells into an eFuse array. Cell 201 differs in that it provides storage for a burned in die identifier (die-ID). At the last stage of the array 205 PData Out 208 and CData Out 209 are passed back to the controller as required in the program and test modes. It should be noted that nodes labeled Cell Out (e.g. 206 and 207) provide a single bit digital output representing the state of that cell, both in the programmed state and in the soft test state. The soft test state gives a non-permanent condition that emulates the state that would have been established after the fuse is programmed.